In construction of microelectronic devices, it is well known that there is a constant pressure for reduction of device size and/or increase of device capability at a given scale.
In the actual construction of reduced scale devices, attention must be paid to higher precision in configuring the materials from which the device components are formed. Attention must also be paid to the interaction of the various materials used in device construction during the device manufacture process, during device testing, and during device operation. In this regard, finer sized device components are more sensitive to adverse materials interactions since the amount of material forming the component is smaller. For example, an interaction that might have only affected the border area of a large component would affect an entire component of smaller scale (e.g., where the scale of the smaller component is the same size as the border area of the larger component). Thus, reduction in component scale forces consideration of materials interaction problems which could have been viewed as non-critical for larger scale components.
In the context of devices such as MOSFET transistors in semiconductor substrates, various materials are used to form the components of the transistor such as the source and drain diffusion regions, electrical contacts (studs) to the diffusion regions, various dielectric regions, gate conductor, gate oxide, etc. For example, the studs are typically metal (i.e. tungsten) or a highly doped polycrystalline silicon (polysilicon) material whereas the source and drain diffusion regions may be very shallow regions of more precise dopant level in the monocrystalline semiconductor substrate. The successful functioning of the transistor depends in part on the ability of these diverse materials to maintain their original or desirably modified character during manufacture/useful life of the device.
Unfortunately, the nature of these materials is such that unwanted interactions may occur unless otherwise prevented. For example, ultra-shallow junctions (required for scalability of MOSFETs to channel lengths significantly shorter than 100 nm) present challenges to successfully forming contacts to source/drain diffusions.
In particular with ultra-shallow junctions, the contact metallurgy (the conductive stud) is prone to xe2x80x9cspike throughxe2x80x9d to the junction edge, which results in excessive leakage currents. One technique which is commonly employed in the art avoids contact metallurgy xe2x80x9cspike throughxe2x80x9d by forming a locally deep junction in the contact hole prior to the deposition of the conductive stud material. Additionally, in the absence of an additional deeper diffusion, crystal defects are likely to propagate from the interface between the contact metallurgy and the silicon substrate into the depletion region of the source-drain diffusion. These silicon defects also result in increased junction leakage currents. Although this deeper diffusion is spaced away from the gate conductor its presence still degrades the short channel characteristics of the MOSFET, since ultra-short channel MOSFETs are very sensitive to junction depth. Furthermore, because of alignment tolerance the proximity of the deeper diffusion to the gate edge may vary randomly. This results in statistical variation of the electrical characteristics of the MOSFET. Therefore, the prior art technique used for contacting source-drain diffusions does not allow the MOSFET to be scaled in an optimal manner.
Additionally, the contact metallurgy may interact with the monocrystalline semiconductor substrate altering the doping of the diffusion in an undesirable manner. In the case of a tungsten stud, dopant may diffuse from the junction into the stud. This lowers the average doping concentration and increases the resistance of the diffusion. Increased diffusion resistance slows the switching speed of the MOSFET. For a polysilicon stud, which is customarily heavily doped to provide low resistance, dopant from the stud may diffuse into the semiconductor substrate. The out-diffusion from the stud may result in an excessively deep diffusion, which degrades the electrical characteristics (i.e. poorer threshold voltage control, increased off-state leakage current) of the MOSFET.
One approach to avoid unwanted interaction has been to employ an intrinsically conductive compound barrier (e.g. TiN or suicide) between the stud and the shallow source/drain diffusion region. See for example, the discussion in xe2x80x9cFundamentals of Semiconductor Processing Technologiesxe2x80x9d by B. El-Kareh, Kluwer Academic Publishers, (1995), p. 534-546. These modifications may introduce other materials interaction problems and/or add significantly to the cost/complexity of the fabrication process.
Thus, there is a desire for improved contact structures which allow better control of materials interactions to enable construction of reliable reduced scale transistor devices. It is also desired to meet these needs in an economical manner that minimizes or avoids compromise of other device or component properties.
The invention provides technology which enables contact structures of improved reliability and performance. More specifically, the invention enables improved contact between conductive studs and shallow diffusion regions by incorporation of a quantum conductive barrier layer at the interface between the conductive stud and shallow diffusion region.
In one aspect, the invention encompasses a structure on a semiconductor substrate, the structure comprising (a) a shallow doped region in the substrate, and (b) an electrical contact to the shallow doped region, wherein the structure further comprises (c) a quantum conductive barrier layer between the doped region and the electrical contact, the doped region being in electrically connected to the electrical contact through the quantum conductive barrier layer.
The invention further encompasses MOSFET transistor structures containing the quantum conductive barriers of the invention at the interfaces between the conductive studs and the source and drain diffusion regions.
In another aspect, the invention encompasses a method of forming a structure on a semiconductor substrate, the structure comprising (a) a shallow doped region in the substrate, (b) an electrical contact to the shallow doped region, and (c) a quantum conductive barrier layer between the doped region and said electrical contact, the method comprising:
(a) providing a monocrystalline semiconductor substrate having a shallow doped region with an exposed surface,
(b) forming a quantum conductive layer on the exposed surface, and
(c) forming a conductive contact over the quantum conductive layer.
Preferred quantum conductive barrier layer materials are silicon nitride or silicon oxynitride. The quantum conductive layer(s) is preferably formed by reacting the exposed surface of the shallow doped region with a nitrogen compound.
These and other aspects of the invention are described in further detail below.